In the recent past, a few lightweight stream ciphers have been implemented for real applications. It is pertinent to note that the implementation of such reliable cryptographic primitives is extremely complicated in practice that requires small processing capacity, low volume, low area, and low power consumption. Developing a software-based synchronous stream cipher is reduced to building a pseudo-random sequence generator with specified cryptographic properties. Symmetric key cryptography is the most commonly used primitive and stream cipher, in particular, meets the requirement of such algorithms. The proposed method is validated in terms of randomness using the statistical test suite provided by National Institute of Standards and Technology (NIST).

The design possess good security and periodicity for the keystream generated. The proposed design is implemented for 8 bit, 16 bit and 128 bit key sizes in FPGA platform. In this paper, the Cyclic Redundancy Check (CRC) hash circuit is combined with the normal LFSR circuit and the keystream is generated by the CRC circuit. In such cases the security of the PRNG depends on the hash function used and the way in which it is used. The commonly used Linear Feedback Shift Register (LFSR) structures with inherent linearity can be used along with hash function based Pseudo Random Number Generator (PRNG) structures to increase periodicity and throughput. Primitive and irreducible polynomials are well tabulated.Stream ciphers based on hash functions are less complex in hardware and provides better security in embedded systems having space constraints.

1+1=0, 0-1=1, etcĪll primitive polynomials are irreducible but the converse is not true! Note the above polynomials are in GF(2) so the only elements are 0,1. Irreducible: Cannot be factored, see example: If the generator is not primitive, possible states (combinations of the register values) will be skipped and the sequence will be less than $2^N-1$ in length before repeating. Primitive: Repeated multiplying by x (representing a shift of one position in the shift register) will generate every possible state (except for the all 0 state).

This is assuming that you are using a maximum length sequence in the implementation of your shift register, which means the generator polynomial is both primitive and irreducible in GF(2). The duration of the linear feedback shift register (LFSR) in number of 'chips' is $2^N-1$ where N is the number of states in the shift register (and order of the generator polynomial), and chips refers to each unique output that is generated in the sequence.

Linear feedback shift register abel